Packet Architects C, PAC for short, is a language specifically developed to make it easy to design hardware that processes packets at very high speeds and with minimal hardware. This is done without the need to write in a low-level hardware description language (Verilog/VHDL).
The PAC language is a general purpose language and enables any kind of packet system to be developed, for example Ethernet, IP, Fibre Channel, Infiniband or even OTN frames. The language offers an easy to read and easy to understand C-like syntax with some additional constructs for implementation of RAMs/CAMs for packet tables and to simplify the interface with software running on a on- or off-chip CPU.
PAC simplifies the description of the packet processing logic but to get efficient hardware the PAC application code is converted to highly efficient pipe-lined logic using a high-level synthesis system developed specifically for the language. The performance of the packet processing logic can therefore be extremely high with very limited design effort. By changing the synthesis constraints the pipeline is automatically optimized to match the requirements. This makes it easy to find a good balance between performance and area whether you’re targeting very high performance or low area.
PAC has a complete development environment with simulator and synthesis tool. The output from the tool-chain is plain synthesizable Verilog.
The ease of using PAC combined with the automatic pipeline synthesis enables a 10x speedup in development time compared to traditional ways of designing your packet processing in an HDL language.
PAC is not intended for taking any C program and turning it into hardware. It is a high level language that is used instead of VHDL/Verilog for describing packet processing hardware.