The FlexSwitch IP is primarily designed to support Switching, Routing and Software Defined Networking (SDN) for Ethernet, but it can easily be used for any packet based processing technologies.
The packet processing is developed in the PAC language. By using a custom language and an in-house high-level synthesis tool flow we achieve a quick turnaround while maintaining excellent area and performance.
Currently available off-the-shelf IP is a complete standard conforming Ethernet L2/L3 switch/router supporting aggregate bandwidth of many 100 Gbit/s in a mid range FPGA, and many Tbit/s when implemented in an ASIC.
The FlexSwitch IP is designed to support custom port speeds up to 1 Terabit/s. Off-the-shelf IP supports standard Ethernet speeds from 100 Mbit/s to 100 Gbit/s.
Reference design for 8x10G Ethernet L2 switch using Xilinx Virtex 690T device is available using only a 20% of this devices logic.
We offer design services to help you in designing optimal packet processing systems such as switches, routers or other packet based systems
2021 – A record year!
2021 has been a record year for PacketArc! We have reached new highs both in delivered ASIC and FPGA cores, and in new customer interest. So things are looking good for 2022 as well!
ASIC design win!
The first quarter of 2021 saw us deliver the first of five ASIC cores to a new customer! The five cores span a range of bandwidths and feature sets for industrial, Enterprise, SOHO, and automotive applications.
Activities second half of 2020
The second half of 2020 was interesting times, seeing us deliver aerospace cores to three new customers! One of the cores had multiple 100G ports in a mid-range FPGA. We also did our first foray into custom protocols, with cores for a high performance wireless chipset.
Activities first half of 2020
Late 2019 and the first half of 2020 saw us fully occupied in customer projects, some of which panned out, and others that were torpedoed by the pandemic.
Activities in 2019-Q3
This quarter we have focused on timing optimization and hierarchy restructuring to simplify floorplanning and P&R. Therefore there are no new, cool features released this quarter.
New IP release 2019-Q2
- Meter / Marker / Policer (MMP) compliant with MEF, DiffServ
- Software C-model of complete switch/router for use in software development, verification or IP evaluation.
- C-API enhanced with functions to simplify accessing hash table entries.
New IP release 2019-Q1
- C-software API released
- FPGA based evaluation platform available purchase or loan
- Added support for Achronix and Microsemi FPGAs
- New resource manager with queue guarantees for the packet buffer
- Improved statistics for debugging
- Verilator is now our main simulator
PacketArc IP is used to demonstrate multi-threaded simulation speed-up
The impressive open-source simulator Verilator now in version 4 supports multi-threading. The developer Wilson Snyder needed a large real-world design to benchmark the performance, and we were happy to give him an IP core to play with.
And it is looking good! See slides 17 and forward in the presentation from ORConf 2018:
Verilator 4.0: Open Simulation Goes Multithreaded
Design win: High-performance L3/MPLS router
We are thrilled to announce that in our largest deal to date our IP will be used to produce a high-performance L3/MPLS router ASIC with multiple 100G Ethernet ports!
Cambium Networks and Packet Architects AB announce that Cambium Networks PTP 700 platform from will use Ethernet switch IP from Packet Architects AB.
Elektroniktidningen: Switchar utan dödkött
The Swedish magazine Elektroniktidningen publishes an extensive article about Packet Architects.
Swedish magazine covers Packet Architects.