At PacketArc we build high-performance Ethernet switch IP cores for packet based communication in FPGA or ASIC technology. All of our IPs are based on an in-house generator we call FlexSwitch. The output from FlexSwitch is datasheet, C-API and verilog source code for the IP Cores.

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The FlexSwitch IP is primarily designed to support Switching, Routing and Software Defined Networking (SDN) for Ethernet, but it can easily be used for any packet based processing technologies.

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The packet processing is developed in the PAC language. By using a custom language and an in-house high-level synthesis tool flow we achieve a quick turnaround while maintaining excellent area and performance.

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Currently available off-the-shelf IP is a complete standard conforming Ethernet L2/L3 switch/router supporting aggregate bandwidth of many 100 Gbit/s in a mid range FPGA, and many Tbit/s when implemented in an ASIC.

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The FlexSwitch IP is designed to support custom port speeds up to 1 Terabit/s. Off-the-shelf IP supports standard Ethernet speeds from 100 Mbit/s to 100 Gbit/s.

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Reference design for 8x10G Ethernet L2 switch using Xilinx Virtex 690T device is available using only a 20% of this devices logic.

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We offer design services to help you in designing optimal packet processing systems such as switches, routers or other packet based systems